Thesis: Zynq (TM)

The Zynq^TM Project consists of the work I will be doing for my thesis as part of the System Chip Design Laboratory (SCDL), a research facility at Temple's College of Engineering that specializes in and strongly advocates for research in reconfigurable System-On-Chip (SOC) architectures, especially programmable logic (PL) such as Field Programmable Gate Arrays (FPGA). The trademarked term "Zynq" comes from the All Programmable (AP) technology on which the Zynq Project depends: The Zynq-7000 Extensible Processing Platform (EPP).

The Zynq-7000 EPP is an integrated circuit (IC) developed by Xilinx and that combines programmable logic (PL) with a processing system (PS) at the IC's center. Specifically, the programmable logic is a FPGA and the processing system is a Dual-core ARM Cortex-A9 processor which can run various Operating Systems (OS), including Real Time OSs (RTOS). The Zynq-7000 EPP's Dual-core ARM processor can support both Symmetric (SMP) and Asymmetric (AMP) Multiprocessing modes, though this project is only concerned with running the RTOS in AMP. Apart from the PL and PS, the Zynq EPP's also includes many peripheral interfaces and utilizes a SoC bus architecture built in accordance to the Advanced Microcontroller Bus Architecture (AMBA) Advance eXtensible Interface (AXI) 4 for communication among the Zynq EPP's ARM Cortex-A9 MPCore processor, FPGA fabric, and other inner-components. Xilinx has also released support for the Zynq EPP and other series 7 devices in the Vivado Design Suite, an Electronic Design Automation (EDA) that provides many powerful tools for analyzing and enhancing hardware performance and High Level Behavioral Synthesis (HLS), the process of converting an algorithm written in a Hardware Description Language (HDL) to a digital form that carries out the same behavior. Xilinx's Software Development Kit (SDK) is the integrated development environment intended for the Zynq EPP's (i.e. ARM processor) software development in C or C++.